A semiconductor non-volatile storage device has such a characteristic that information stored therein would not volatile even when the power switch is turned off. Conventionally, semiconductor non-volatile storage devices have been used as storage devices for storing voice or image data. For that reason, they have been developed focusing on higher density and non-volatility. In recent years, among semiconductor non-volatile storage devices, those of “NOR-type structure” having an excellent property of fast operation have been supplied for storing cellular phone program codes and other purposes and a their market is rapidly growing.
FIG. 1 is a diagram of a circuit having a NOR-type structure. In this figure, only two local bit lines LB1 and LB2 are shown in a memory cell array region CA. The common regions of the diffusion layers of the memory cells arrayed into rows to which a source drain path is serially connected, are connected to the local bit lines LB1 or LB2 alternately. The remaining common regions of the diffusion layers are all connected to the memory source terminal VSM. In general, the potential of the memory source terminal VSAM is assumed to be 0V. 32 Word lines W01 to W32 are assured to be used for selecting individual memory cells in the figure.
Now, the procedure for reading out information stored in, for example the memory cell connected to the local bit line LB1, is described. A positive potential is applied to a selection signal line SwA1 and a selection transistor ST1 is turned on. The local bit line LB1 is pre-charged via a global bit line GB1. Then, the potential on the desired word line (any of W01 to W32) is raised for selection. For example, the selection of the word line W01 allows information stored in the memory cell MC01 to be read out. If the information stored in the memory cell MC01 with its associated gate potential raised is “0”, namely, a threshold for the memory cell MC01 is high, the memory cell MC01 is not turned on with no change in pre-charge potential. On the other hand, if the stored information is “1”, namely, if the threshold for the memory cell MC01 is low, the memory cell MC01 is turned on and the potential on the local bit line LB1 is supplied to the global bit line GB1 via the memory cell MC01, being detected in a sense amplifier SA1.
Among various types of sense amplifiers being used, a single-end type of sense amplifier SA1, which is well known, is shown in the figure. This sense amplifier SA1 is composed of two inverters INV1 and INV2, a transistor NM, and a load resistance REG. Usually, the local bit lines LB1 and LB2, each of which is composed of a low-resistance metal wire, have lower parasitic resistances compared with other types of non-volatile storage devices. For that reason, among the sense amplifiers for the semiconductor non-volatile storage devices, this type is most suitable for fast information readout. Note that the operation of the sense amplifier SA1 will be explained later in the description of one preferred embodiment of the present invention in reference to FIG. 3 shown.
FIG. 2 is a plan layout diagram of the circuit structure shown in FIG. 1. In FIG. 2, a reference symbol CA indicates a memory cell array region and ST1G and ST2G are corresponding to gate electrodes of the selection transistors ST1 and ST2, each of which connects a signal line from a global bit line GB1 to the local bit lines LB1 and LB2, respectively, namely the selections signal lines SWA1 and SWA2 shown in FIG. 1. VIA1 is a contact hole, which connects the gate electrode or the diffusion layer to the first metal wiring layer, for example an interlayer via hole, which connects the local bit lines LB1 and LB2 to the drain diffusion layer region of the memory cell. On the other hand, VIA2 is a contact hole, which connects the metal wiring in the first layer to that in the second layer, for example an interlayer via hole, which connects the global bit line GB1 to the local bit lines LB1 and LB2. Note that the layout of the sense amplifier element is omitted.
To connect a signal line to the local bit line LB1, voltage is applied to the selection signal line SWA1 and to connect the signal line to the local bit line LB2, voltage is applied to the selection signal line SWA2. VSSCOM is the source diffusion region of the memory cell, which is commonly connected to a memory source terminal VSM so that potential may be applied. In general, the applied potential is 0 V.
In the case of being used for storing program codes, unlike for storage use, memory cells need to output information as quickly as possible in line with a logical circuit operating at a high speed. It is difficult even for the above-mentioned storage device having a NOR-type structure suitable for fast information readout to keep in line with the existing logical circuits operating at high speeds. The reason is that an on current flowing through the non-volatile storage cells (hereafter, simply referred to as “memory cells or memory transistors”) is too small to drive the parasitic load capacitance on the signal wirings quickly.
System performance cannot be enhanced unless the semiconductor non-volatile storage device containing program codes is capable of outputting information at a speed in line with the processor's operation speed. Alternatively, such a method may be assumed that for the system to be ready for run, the information stored in the semiconductor non-volatile storage device is read out into another fast storage device. In the case of the mobile devices including the mentioned-above one, however, this method causes such problems as larger device sizes and increased costs, meaning that it is anything but a best bet.
In this context, the objective of the present invention is to provide a semiconductor non-volatile storage device suitable for mobile device use, which can be used in reading out program codes at a high speed.